As the ASIC (Application Specific Integrated Circuit) industry moves forward with teach technology mode (for example from 90 nm to 65 nm to 45 nm), the necessity for Low Power Design techniques increases. One Low Power technique involves powering down unused portion of the design to save both dynamic and leakage power. When design parts are powered down, care must be taken between the powered down outputs and powered on inputs. An isolation cell may be used to prevent short circuit currents. The traditional isolation cell for single voltage designs (AND, OR gates) address this issue; however, the traditional isolation cell can complicate Design For Test (DFT) coverage issues and result in higher design area overhead.